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TAS5760MDAPR bảng dữ liệu(PDF) 33 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  General-Purpose I2S Input Class-D Amplifier
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TAS5760M
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SLOS772D – JULY 2013 – REVISED JULY 2015
Device Functional Modes (continued)
Table 3 details the supported SCLK rates for each of the available sample rate and MCLK rate configurations.
For each fS and MCLK rate, the supported SCLK rates are shown and are represented in multiples of the sample
rate, which is written as "x fS".
Table 3. Supported SCLK Rates in Hardware Control Mode (Single Speed Mode)
MCLK Rate
[x fS]
128
192
256
384
512
Sample Rate [kHz]
12
N/S
N/S
N/S
N/S
32, 48, 64
16
N/S
N/S
32, 48, 64
32, 48, 64
32, 48, 64
24
N/S
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
38
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
44.1
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
48
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
9.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
The TAS5760M has a soft clipper that can be used to clip the output voltage level below the supply rail. When
this circuit is active, the amplifier operates as if it was powered by a lower supply voltage, and thereby enters into
clipping sooner than if the circuit was not active. The result is clipping behavior very similar to that of clipping at
the PVDD rail, in contrast to the digital clipper behavior which occurs in the oversampled domain of the digital
path. The point at which clipping begins is controlled by a resistor divider from GVDD_REG to ground, which sets
the voltage at the SFT_CLIP pin. The precision of the threshold at which clipping occurs is dependent upon the
voltage level at the SFT_CLIP pin. Because of this, increasing the precision of the resistors used to create the
voltage divider, or using an external reference will increase the precision of the point at which the device enters
into clipping. To ensure stability, and soften the edges of the clipping event, a capacitor should be connected
from pin SFT_CLIP to ground.
Figure 45. Soft Clipper Example Wave Form
To move the output stage into clipping, the soft clipper circuit limits the duty cycle of the output PWM pulses to a
fixed maximum value. After filtering this limit applied to the duty cycle resembles a clipping event at a voltage
below that of the PVDD level. The peak voltage level attainable when the soft clipper circuit is active, called VP in
the example below, is approximately 4 times the voltage at the SFT_CLIP pin, noted as VSFT_CLIP. This voltage
can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance,
as shown in the equation below.
Copyright © 2013–2015, Texas Instruments Incorporated
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