AS3955 datasheet(57/111 Pages) AMSCO

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ams Datasheet

Page 57

[v1-01] 2015-Apr-29

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AS3955 − Detailed Description

Figure 58:

IO Signals to Controller

Writing Data to Addressable Registers

(Register Write Mode)

Following figures show waveforms of writing a single byte and

writing multiple bytes with auto-incrementing address. After

the SPI operation mode bits, the address of starting register to

be written is provided. Then one or more data bytes are

transferred from the SPI, always MSB first. The data byte is

written in register on falling edge of its last clock. In case the

communication is terminated by putting /SS high before a

packet of 8 bits composing one byte is sent, writing of this

address does not exist or it is a read-only register, no write is

performed.

Figure 59:

SPI Communication: Writing a Single Register

MOSI

MISO

MOSI

μC

AS3955

MOSI

MISO

I/O

μC

AS3955

Separate SPI Input and Output Signals to Controller

Bidirectional Data IO Signal to Controller

SCLK raising

edge Data is

transfered

from µC

SCLK falling

edge Data is

sampled

Data is moved to

Address

A4-A0

/SS rising

edge signals

end of WRITE

Mode

Three

leading bits

indicate Mode

/SS

SCLK

MOSI

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