LIS2DS12 datasheet(34/68 Pages) STMICROELECTRONICS

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Digital interfaces

LIS2DS12

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DocID027753 Rev 4

6.1.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a high-to-low transition on the data line while the SCL line is held high. After this

has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the master.

The Slave Address (SAD) associated to the LIS2DS12 is 00111xxb where the xx bits are

modified by the SA0/SDO pin in order to modify the device address. If the SA0/SDO pin is

connected to the supply voltage, the address is 0011101b, otherwise if the SA0/SDO pin is

connected to ground, the address is 0011110b. This solution permits to connect and

address two different accelerometers to the same I2C lines.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line low so that it

remains stable low during the high period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded inside the LIS2DS12 behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a slave address is sent. Once a

slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the

7 LSb represents the actual register address while the CTRL2 (21h) (IF_ADD_INC) bit

defines the address increment.

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes. If the bit is ‘0’ (Write)

the master will transmit to the slave with direction unchanged. Table 17 explains how the

SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Table 17. SAD+Read/Write patterns

Command

SAD[6:2]

SAD[1] = SA0

SAD[0] = SA0

R/W

SAD+R/W

Read

00111

00111101

Write

00111

00111100

Read

00111

00111011

Write

00111

00111010

Table 18. Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

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