PCF7991AT datasheet(9/19 Pages) ETC2

9 / 19 page

printed 1998 Apr 20

Philips Semiconductors

Product Speciﬁcation (Rev. 1998 Apr 20)

Advanced Basestation IC

PCF7991AT

8.8.1

SERIAL INTERFACE MODE

The serial interfaces supports two modes of operation,

filtered and non-filtered communication.

If MODE is connected to VSS no filtering is applied and the

state of the interface signals is directly available at the

internal circuitry. The maximum data rate of the serial

interface is limited by the set-up and hold time as specified

(see Chapter 12).

If MODE is connected to VDD, digital filtering of SCLK and

DIN is performed offering improved immunity against

glitches on these interface signals. This mode of operation

is intended for use for so called ‘Active Antenna

Applications’, where the PCF7991AT and the

microcontroller have to communicate via long interface

wires. The digital filtering is provided by sampling the

SCLK and DIN inputs at a rate of 1/fTX, 8 µs typically. The

internal state of these signals is updated only, if two

successive samples are equal. Due to the sampling

operation a state change at the SCLK or DIN input is

delayed at least by 16

µs before it is recognized by the

internal circuitry. If DIN and DOUT are connected to each

other to form a two wire communication link, the filtering

delay between DIN and DOUT must be considered. Due to

the digital filtering, the maximum serial interface data rate

is limited to approximately 30 kbit/sec.

If digital filtering of SCLK and DIN is enabled and the device

has been forced into Power-down mode, this mode can be

terminated by setting SCLK to LOW and DIN unequal to the

status bit TXDIS (see Table 10). As a result the XTAL

oscillator is restarted and the configuration bit PD_MODE

is cleared, which causes the device to enter Idle mode.

Fig.4 Serial Interface Timing.

DIN

DOUT

SCLK

initialization

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