PCF7991AT datasheet(8/19 Pages) ETC2

8 / 19 page

printed 1998 Apr 20

Philips Semiconductors

Product Speciﬁcation (Rev. 1998 Apr 20)

Advanced Basestation IC

PCF7991AT

low pass filter. Miss-tuning of the resonance antenna

circuit by component spreads or due to ambient

temperature changes results in a change of the phase

relationship. The actual phase relationship is determined

by a READ_PHASE command (see Table 6) and used to

calculate the optimum receive signal sampling time with

support of an external microcontroller.

8.5.4

DETERMINING THE SAMPLING TIME

Measurement, calculation and setting of the sampling time

is typically implemented during system power-up

initialization when the transponder is also in its power-up

sequence not sending any data. As soon as the oscillator

and resonance antenna circuit are settled a phase

measurement is initiated and the sampling time

determined according to the following relation:

TS = 2 * TANT + TOFFSET

Receive signal sampling time

TANT

Actual phase measurement

TOFFSET

Offset that accounts for the phase shift due

to the antenna tap voltage attenuation and

low pass filtering

After setting the sampling time the receiver has to settle

before data can be demodulated and digitized properly.

8.5.5

DATA AMPLITUDE COMPARISON

For advanced receiver sampling time optimization the

demodulated data signal strength can be weighted by

amplitude comparison and the result reported in the status

bit AMPCOMP (see Table 13).

When the ACQAMP control bit (see Table 10) is set by a

SET_CONFIG_PAGE command, the actual demodulated

data signal amplitude is stored as reference. After

resetting the ACQAMP control bit the status bit

AMPCOMP is set, when the actual data signal amplitude

is larger than the stored reference otherwise it is cleared.

8.5.6

SYSTEM DIAGNOSTICS

In order to detect an antenna short or open condition the

receiver input voltage at the RX-pin is monitored and an

antenna fail condition is reported in the status bit ANTFAIL,

(see Table 13). If the receiver input voltage does not

exceed the diagnostic threshold level VDTH (see

Chapter 11), the status bit ANTFAIL is set, otherwise it is

cleared. The status bit is updated once per antenna carrier

period and can be read by a GET_CONFIG_Page 2 or 3

command (see Table 13). The status bit is undefined in

Power-down or Idle mode, during the oscillator start-up

time and when the antenna drivers are disabled.

Advanced system diagnostics are feasible by considering

the phase measurement information also.

8.6

Power-on reset

The device generates an internal power-on reset to

initialize the chip after power-on or power fail condition. As

a result the control register is initialized according to

Table 11.

8.7

Power-down modes

After a power-on reset condition the device operates in

ACTIVE mode. The PCF7991AT supports an Idle and

Power-down mode for power saving means. The mode of

operation is determined by control bits addressed by an

SET_CONFIG_PAGE 1 command (see Table 10).

In Idle mode only the oscillator and a minimum of other

circuitry is active. In Power-down mode the device is in

OFF state completely. The serial interface is operational in

any case in order to provide access to the control register.

8.8

Serial Interface

The communication between the PCF7991AT and the

microcontroller is done via a three wire digital interface.

The interface is used to issue commands for writing and

reading of device configuration data and for writing and

reading to the transponder in one of the transparent

modes (READ_TAG, WRITE_TAG). Device configuration

is stored in a control register with read back feature.

The interface is operated by the following signals:

SCLK

Clock

DIN

Data Input

DOUT

Data Output

SCLK and DIN are realized as Schmitt-Trigger inputs.

DOUT is an open drain output with internal pullup resistor.

Any communication between the PCF7991AT and the

microcontroller begins with an initialization of the serial

interface before the desired command can be issued. The

interface initialization condition is a low-to-high transition

of the signal DIN while SCLK is high (see Fig.4).

All commands are transmitted to the PCF7991AT serial

interface starting with Most Significant Bit (MSB). DIN is

latched with a high state at SCLK. DOUT is valid during the

high state of SCLK (MODE pin connected to VSS).

DOUT and DIN may be connected to each other in order to

form a two wire communication link with the

microcontroller.

PCF7991AT bảng dữ liệu(PDF) 8 Page - List of Unclassifed Manufacturers

PCF7991AT bảng dữ liệu(HTML) 8 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

bảng dữ liệu tải về

Link URL