ATmega16 datasheet(159/315 Pages) ATMEL

159 / 315 page

159

ATmega16(L)

2466E–AVR–10/02

do not contain data to be transmitted. When disabled, the transmitter will no longer over-

ride the TxD port.

• Bit 2 – UCSZ2: Character Size

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits

(Character Size) in a frame the receiver and transmitter use.

• Bit 1 – RXB8: Receive Data Bit 8

RXB8 is the ninth data bit of the received character when operating with serial frames

with nine data bits. Must be read before reading the low bits from UDR.

• Bit 0 – TXB8: Transmit Data Bit 8

TXB8 is the ninth data bit in the character to be transmitted when operating with serial

frames with nine data bits. Must be written before writing the low bits to UDR.

USART Control and Status

The UCSRC Register shares the same I/O location as the UBRRH Register. See the

“Accessing UBRRH/ UCSRC Registers” on page 155 section which describes how to

access this register.

• Bit 7 – URSEL: Register Select

This bit selects between accessing the UCSRC or the UBRRH Register. It is read as

one when reading UCSRC. The URSEL must be one when writing the UCSRC.

• Bit 6 – UMSEL: USART Mode Select

This bit selects between Asynchronous and Synchronous mode of operation.

Bit

765

432

URSEL

UMSEL

UPM1

UPM0

USBS

UCSZ1

UCSZ0

UCPOL

UCSRC

Read/Write

R/W

Initial Value

Table 63. UMSEL Bit Settings

UMSEL

Mode

Asynchronous Operation

Synchronous Operation

ATMEGA16 bảng dữ liệu(PDF) 159 Page - ATMEL Corporation

ATMEGA16 bảng dữ liệu(HTML) 159 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL