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ATmega16(L)

2466E–AVR–10/02

I/O Ports

Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital

I/O ports. This means that the direction of one port pin can be changed without uninten-

tionally changing the direction of any other pin with the SBI and CBI instructions. The

same applies when changing drive value (if configured as output) or enabling/disabling

of pull-up resistors (if configured as input). Each output buffer has symmetrical drive

characteristics with both high sink and source capability. The pin driver is strong enough

to drive LED displays directly. All port pins have individually selectable pull-up resistors

with a supply-voltage invariant resistance. All I/O pins have protection diodes to both

CC and Ground as indicated in Figure 22. Refer to “Electrical Characteristics” on page

285 for a complete list of parameters.

Figure 22. I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower case

“x” represents the numbering letter for the port, and a lower case “n” represents the bit

number. However, when using the register or bit defines in a program, the precise form

must be used. i.e., PORTB3 for bit no. 3 in Port B, here documented generally as

PORTxn. The physical I/O Registers and bit locations are listed in “Register Description

for I/O Ports” on page 62.

Three I/O memory address locations are allocated for each port, one each for the Data

Port Input Pins I/O location is read only, while the Data Register and the Data Direction

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on

page 48. Most port pins are multiplexed with alternate functions for the peripheral fea-

tures on the device. How each alternate function interferes with the port pin is described

in “Alternate Port Functions” on page 52. Refer to the individual module sections for a

full description of the alternate functions.

Note that enabling the alternate function of some of the port pins does not affect the use

of the other pins in the port as general digital I/O.

Logic

See Figure 23

"General Digital I/O" for

Details

Pxn

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