LE25S161PCTXG datasheet(8/54 Pages) ONSEMI

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LE25S161

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5. Pin Description

Sy mbol

Pin Name

Description

Chip select

The dev ice becomes activ e when the logic lev el of this pin is low; it is deselected and placed in

standby status when the logic lev el of the pin is high.

SCK

Serial clock

This pin controls the data input/output timing.

The input data and addresses are latched sy nchronized to the rising edge of the serial clock, and

the data is output sy nchronized to the f alling edge of the serial clock.

(SIO0)

Serial data input

(Serial data input output)

I/O

The data and addresses are input f rom this pin, and latched internally sy nchronized to the rising

edge of the serial clock.

(It changes into input/output pin during the Dual operation.)

(SIO1)

Serial data output

(Serial data input output)

I/O

The data stored inside the dev ice is output f rom this pin sy nchronized to the f alling edge of the

serial clock.

( It changes into input/output pin during the Dual operation.)

Write protect

The Write Status Register Protect (SRWP) takes ef f ect when the logic lev el of this pin is low.

HOLD

Hold

Serial communication is suspended when the logic lev el of this pin is low.

VDD

Power supply

This pin supplies the 1.65 to 1.95V supply v oltage.

VSS

Ground

This pin supplies the 0V supply v oltage.

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