SD6830P datasheet(13/34 Pages) AUK

13 / 34 page

KSI-W002-000

6.12 Power-on reset

The SD6830 incorporates an on-chip power-on reset circuitry which provides internal chip

reset for most power-up situations. The power-on reset circuit and the watchdog timer are

closely related. On power-up the power-on reset circuit is active and watchdog timer is

reset. After the reset time, which is in proportion to the rate of rise of VDD, watchdog timer

begins counting. After the oscillator stabilization time, which is typically 27mS in

SYS=455KHz, program execution proceeds from reset address (000H).

Figure 6-5. Built-in Power-on Reset

6.13 Stop mode

The SD6830 support the stop mode to reduce power consumption. This mode is entered

when the STOP instruction is executed during key inputs are not active. Activating any key

inputs (Port D, Port E) the device is awakened from stop mode and restarts to operate from

reset address. When the device is released from stop mode, following module

set to appropriate value in reset routine: PORT G and PORT K.

In stop mode, the oscillator is stopped and the each port state is as follows.

Port C/REM become inactive state. (

for including I.R.LED driver,

after the reset release)

Port G and Port K retain previous state.

SD6830

VDD

VSS

Internal

/POR

DMC6830

7pF

2Mohm

RESET TIME

1.8V

0.3VDD

VDD

VDD PIN

Internal

/POR

SD6830

SD6830P bảng dữ liệu(PDF) 13 Page - AUK corp