CS4328 datasheet(9/31 Pages) CIRRUS

9 / 31 page

mute which can be activated by forcing the

CALI pin high. Figure 7 shows how to imple-

ment a -50 dB mute using an OR gate. The

propagation of the gate will be the only delay in

moving the CS4328 to a muted state.

The second mute option is a two stage operation

which involves forcing SDATAI to 0 using an

AND gate as shown in Figure 8. The first mute

occurs following 33 LRCK cycles when the 0 in-

put data propagates to the output of the DAC.

The rms noise present at the output will typically

be 93 dB below fullscale. Following a total of

4096 LRCK cycles with 0 input data the output

of the CS4328 will mute and lower the output

rms noise to a minimum of 120 dB below

fullscale. Upon release of the MUTE command

and non-zero input data the CS4328 output mute

will immediately release. However, 33 LRCK

cycles are required for input data to propagate to

the output of the CS4328.

Grounding and Power Supply Decoupling

As with any high resolution converter, the

CS4328 requires careful attention to power sup-

ply and grounding arrangements to optimize

performance. Figure 1 shows the recommended

power arrangements with VA+ connected to a

clean +5 volt supply and VA- connected to a

clean -5 volt supply. VD+, which powers the

digital interpolation filter and delta-sigma modu-

lator, may be powered from the system +5 volt

logic supply. Decoupling capacitors should be

located as near to the CS4328 as possible.

The printed circuit board layout should have

separate analog and digital regions with individ-

ual ground planes. The CS4328 should straddle

th e gro un d p lane break as shown on the

CDB4328 Evaluation board. Optional jumpers

for connecting these planes should be included

near the DAC, where power is brought on to the

board and near the regulators. All signals, espe-

cially clocks, should be kept away from the

VREF- pin to avoid unwanted coupling into the

CS4328. The VREF- decoupling capacitors, par-

ticularly the 0.1

µF, must be positioned to

minimize the electrical path from VREF- to

Pin 1 AGND and to minimize the path between

VREF- and the capacitors. Extensive use of

ground plane fill on both the analog and digital

sections of the circuit board will yield large re-

ductions in radiated noise effects. An application

note "Layout and Design Rules for Data Con-

verters" is printed in the Application Note

section of this book.

Analog Output and Filtering

Full scale analog output for each channel is typi-

cally 4V peak-to-peak. The analog outputs can

drive load impedances as low as 600

Ω and are

short-circuit protected to 20mA.

The C S4328 an alog filter is a 5th order

switched-capacitor filter followed by a second-

o rd er

continuous-time

fi lt er.

The

switched-capacitor filter is clock dependent and

will scale with the IWR frequency. The continu-

ous-time filter is fixed and not related to IWR. A

low-pass filter consisting of a 51

Ω resistor and a

.01

µF NPO capacitor is recommended on the

analog outputs.

MUTE

CALO

CALI

CS4328

Figure 7. -50dB Muting

MUTE

SDATAI

CS4328

DATA

_____

Figure 8. -120 dB Muting

CS4328

DS62F3

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