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CS4328 bảng dữ liệu(PDF) 7 Page - Cirrus Logic |
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CS4328 bảng dữ liệu(HTML) 7 Page - Cirrus Logic |
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7 / 31 page ![]() latch data. Table 2 lists the four formats, along with the associated figure number. Format 0 is compatible with existing 16-bit D/A converters and digital filters. Format 1 is an 18-bit version of format 0. Format 2 is similar to Crystal ADCs and many DSP serial ports. Format 3 is compat- ible with the I 2S serial data protocol. Formats 2 and 3 support 18-bit input or 16-bit followed by two zeros. In all four serial input modes, the se- rial data is MSB-first and 2’s-complement format. Formats 0, 2 and 3 will operate with 16-bit data and 16 BICK pulses as well. See Figure 6 for 1 6 - bit timing. However, th e use of BICK = 64 × IWR is recommended to minimize the possibility of performance degradation result- ing from BICK coupling into VREF-. Reset and Offset Calibration RST is an active low signal that resets the digital filter and the delta-sigma modulator, synchro- nizes LRCK with internal control signals and starts an offset calibration cycle upon exiting re- set. When RST goes low, CALO goes high and stays high until the end of an offset calibration cycle. An offset calibration cycle takes 1024 IWR cycles to complete. CALO must be con- nected to CALI and CMPO must be connected to CMPI for offset calibration. During an offset calibration the analog output is forced to zero. Power-Up Considerations Upon initial application of power to the DAC, offset calibration and digital filter registers will be indeterminate. RST should be low during power-up to activate an internal mute and pre- vent this erroneous information from being output from the DAC. Bringing RST high will begin a calibration cycle and initialize these reg- isters. Muting There are two types of mutes that can be imple- mented with the CS4328. The first is a -50 dB DIF1 DIF0 Mode Figure 00 0 3 01 1 3 10 2 4 11 3 5 Table 2. Digital Input Formats XTI/XTO Reset Status 40 ns minimum 40 ns minimum Exit Reset LRCK "Kickstart" ACK0 RST Figure 2. RESET Cancellation Timing CS4328 DS62F3 7 |
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