LP62S161024 datasheet(2/16 Pages) AMICC

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LP62S161024 Series

Preliminary

16M BIT (1M x 16 / 2M x 8) LOW VOLTAGE CMOS SRAM

PRELIMINARY

(November, 2014, Version 0.0)

AMIC Technology, Corp.

Features

Operating voltage: 2.7V to 3.6V

Access times: 55/70 ns (max.)

Current:

Very low power version: Operating: 50mA (max.)

Standby:

μA (max.)

Full static operation, no clock or refreshing required

All inputs and outputs are directly TTL-compatible

Common I/O using three-state output

Data retention voltage: 2.0V (min.)

Available in 48-pin TSOP (I) and 48-ball CSP (6 x 8 mm)

packages

All Pb-free (Lead-free) products are RoHS2.0 compliant

The TSOP (I) package configurable as 1M x 16 or 2M x 8

Static RAM

- BYTE fixed to HIGH, LB controlled I/O0 - I/O7, HB

controlled I/O8 - I/O15

- BYTE fixed to LOW, I/O15 used as address pin, while

I/O8 - I/O14 pins not used

General Description

The LP62S161024 is a low operating current 16,777,216-

bit static random access memory organized as 1,048,576

words by 16 bits and operates on low power voltage from

2.7V to 3.6V. It is built using AMIC's high performance

CMOS process.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

Two chip enable input is provided for POWER-DOWN,

device enable. Two byte enable inputs and an output

enable input are included for easy interfacing.

Data retention is guaranteed at a power supply voltage as

low as 2.0V.

Product Family

Power Dissipation

Product

Family

Operating

Temperature

VCC

Range

Speed

Data Retention

(ICCDR, Typ.)

Standby

(ISB1, Typ.)

Operating

(ICC2, Typ.)

Package

Type

LP62S161024

°C ~ +70°C

2.7V~3.6V

55ns / 70ns

0.3

μA

0.5

μA

4mA

48 TSOP (I)

48-ball CSP

LP62S161024(I)

-40

°C ~ +85°C

2.7V~3.6V

55ns / 70ns

0.3

μA

0.5

μA

4mA

48 TSOP (I)

48-ball CSP

1. Typical values are measured at VCC = 3.0V, TA = 25

°C and not 100% tested.

2. Data retention current VCC = 2.0V.

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