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ASM1832F bảng dữ liệu(PDF) 4 Page - ON Semiconductor

tên linh kiện ASM1832F
Giải thích chi tiết về linh kiện  Power Supply Monitor and Reset Circuit
PDF  9 Pages
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nhà sản xuất  ONSEMI [ON Semiconductor]
Trang chủ  http://www.onsemi.com
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ASM1832F bảng dữ liệu(HTML) 4 Page - ON Semiconductor

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ASM1832
http://onsemi.com
4
Detailed Description
The ASM1832 monitors the microprocessor or
microcontroller power supply and issues reset signals, both
active HIGH and active LOW, that halt processor operation
whenever the power supply voltage levels are outside a
predetermined tolerance.
RESET and RESET Outputs
RESET and RESET signals are active for a minimum of
250 ms after the supply has returned to in−tolerance level.
This allows the power supply and monitored processor to
stabilize before instruction execution is allowed to begin.
Trip Point Tolerance Selection
The TOL input is used to determine the level VCC can vary
below 3.3 V without asserting a reset. With TOL connected
to VCC, RESET and RESET become active whenever VCC
falls below 2.64 V. RESET and RESET become active when
the VCC falls below 2.98 V if TOL is connected to ground.
After VCC has risen above the trip point set by TOL,
RESET and RESET remain active for a minimum time
period of 250 ms. On power−down, once VCC falls below
the reset threshold RESET stays LOW and is guaranteed to
be 0.4 V or less until VCC drops below 1.2 V. The reset
output on the ASM1832 uses a push−pull drive stage that can
maintain a valid output below 1.2 V. To sink current with
VCC below 1.2 V, a resistor can be connected from the reset
pin (RESET) to Ground. This configuration will give a valid
value on the reset output with VCC approaching 0 V. During
both power up and down, the configuration will draw current
when the RESET is in the high state. The value of 100 K
W
should be adequate to maintain a valid condition. The active
HIGH reset signal is valid down to a VCC level of 1.2 V also.
Table 4.
Tolerance
Select
Tolerance
TRIP Point Voltage (V)
Min
Nom
Max
TOL = VCC
20%
2.47
2.55
2.64
TOL = GND
10%
2.80
2.88
2.97
Figure 3.
Figure 4. Timing Diagram: Power Up
Figure 5. Timing Diagram: Power Down
Application Information
Manual Reset Operation
Push−button switch input, PBRST, allows the user to
override the internal trip point detection circuits and issue
reset signals. The pushbutton input is debounced and is
pulled HIGH through an internal 40 k
W resistor.
When PBRST is held LOW for the minimum time tPB,
both resets become active and remain active for a minimum
time period of 250 ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses
greater than 20 ms. No external pull−up resistor is required,
since PBRST is pulled HIGH by an internal 40 k
W resistor.
The PBRST can be driven from a TTL or CMOS logic line
or shorted to ground with a mechanical switch.



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