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ASM1832F bảng dữ liệu(PDF) 2 Page - ON Semiconductor |
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ASM1832F bảng dữ liệu(HTML) 2 Page - ON Semiconductor |
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2 / 9 page ![]() ASM1832 http://onsemi.com 2 Figure 1. Typical Operating Circuit Figure 2. Block Diagram Table 1. PIN DESCRIPTION Pin # 8−Pin Package Pin Name Function 1 PBRST Debounced manual pushbutton reset input. 2 TD Watchdog time delay selection. (tTD = 150 ms for TD = GND, tTD = 610 ms for TD = Open, and tTD = 1200 ms for TD = VCC). 3 TOL Selects 10% (TOL connected to GND) or 20% (TOL connected to VCC) trip point tolerance. 4 GND Ground. 5 RESET Active HIGH reset output. RESET is active: 1. If VCC falls below the reset voltage trip point. 2. If PBRST is LOW. 3. If ST is not strobed LOW before the timeout period set by TD expires. 4. During power−up. 6 RESET Active LOW reset output. (See RESET). 7 ST Strobe input. 8 VCC 3.3 V power. Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Min Max Unit Voltage on VCC (Note 1) −0.5 7 V Voltage on ST, TD (Note 1) −0.5 VCC + 0.5 V Voltage on PBRST, RESET, RESET (Note 1) −0.5 VCC + 0.5 V Operating Temperature Range −40 +85 °C Soldering Temperature (for 10 sec) +260 °C Storage Temperature −55 +125 °C ESD rating HBM 2 KV MM 200 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Voltages are measured with respect to ground. |
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