MT9V024 datasheet(44/62 Pages) ONSEMI

44 / 62 page

MT9V024_DSRev. G Pub. 4/15 EN

©Semiconductor Components Industries, LLC, 2015.

MT9V024: 1/3-Inch Wide-VGA Digital Image Sensor

Feature Description

Figure 34:

Spatial Illustration of Interlaced Image Readout

When interlaced mode is enabled, the total number of blanking rows are determined by

both Field Blanking register (R0xBF) and Vertical Blanking register (R0x06 or R0xCE).

The followings are their equations.

Field Blanking = R0xBF[7:0]

(EQ 22)

Vertical Blanking = R0x06[8:0] – R0xBF[7:0] (context A) or R0xCE[8:0] – R0xBF[7:0] (context B)

(EQ 23)

with

minimum vertical blanking requirement = 4 (absolute minimum to operate; see Vertical Blanking Registers

description for VBlank minimums for valid image output)

(EQ 24)

Similar to progressive scan, FV is logic LOW during the valid image row only. Binning

should not be used in conjunction with interlaced mode.

P4,1 P4,2 P4,3.....................................P4,n-1 P4,n

P6,0 P6,1 P6,2.....................................P6,n-1 P6,n

00 00 00 .................. 00 00 00

Pm-2,0 Pm-2,2.....................................Pm-2,n-2 Pm-2,n

Pm,2 Pm,2.....................................Pm,n-1 Pm,n

00 00 00 .................. 00 00 00

00 00 00 ..................................... 00 00 00

00 00 00 ............................................................................................. 00 00 00

VALID IMAGE - Even Field

HORIZONTAL

BLANKING

VERTICAL BLANKING

P5,1 P5,2 P5,3.....................................P5,n-1 P5,n

P7,0 P7,1 P7,2.....................................P7,n-1 P7,n

Pm-3,1 Pm-3,2.....................................Pm-3,n-1 Pm-3,n

Pm,1 Pm,1.....................................Pm,n-1 Pm,n

VALID IMAGE - Odd Field

FIELD BLANKING

MT9V024 bảng dữ liệu(PDF) 44 Page - ON Semiconductor