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AR0330 bảng dữ liệu(PDF) 30 Page - ON Semiconductor

tên linh kiện AR0330
Giải thích chi tiết về linh kiện  CMOS Digital Image Sensor
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AR0330_DS Rev. U Pub. 4/15 EN
30
©Semiconductor Components Industries, LLC,2015.
AR0330: 1/3-Inch CMOS Digital Image Sensor
HiSPi Transmitter
Clock Signal
tHCLK is defined as the high clock period, and tLCLK is defined as the low clock period as
shown in Figure 15. The clock duty cycle DCYC is defined as the percentage time the clock
is either high (tHCLK) or low (tLCLK) compared with the clock period T.
Figure 15:
Clock Duty Cycle
(EQ 9)
(EQ 10)
(i.e, 1 UI)
(EQ 11)
(EQ 12)
Figure 16 shows the definition of clock jitter for both the period and the cycle-to-cycle
jitter.
Figure 16:
Clock Jitter
Period Jitter (tCKJIT) is defined as the deviation of the instantaneous clock tPW from an
ideal 1UI. This should be measured for both the clock high period variation tHCLK, and
the clock low period variation tLCLK taking the RMS or 1-sigma standard deviation and
quoting the worse case jitter between tHCLK and tLCLK.
D
CYC 1

t
HCLK
T
--------------
=
D
CYC 0

t
LCLK
T
-------------
=
t
pw
T
2
---
=
Bitrate
1
t
pw
-------
=



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