TC7135 datasheet(6/22 Pages) MICROCHIP

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TC7135

DS21460B-page 6

3.0

DETAILED DESCRIPTION

(All Pin Designations Refer to 28-Pin DIP)

3.1

Dual Slope Conversion Principles

The TC7135 is a dual slope, integrating A/D converter.

An understanding of the dual slope conversion tech-

nique will aid in following the detailed TC7135

operational theory.

The conventional dual slope converter measurement

cycle has two distinct phases:

Input signal integration

Reference voltage integration (de-integration)

The input signal being converted is integrated for a

fixed time period. Time is measured by counting clock

pulses. An opposite polarity constant reference voltage

is then integrated until the integrator output voltage

returns to zero. The reference integration time is

directly proportional to the input signal.

In a simple dual slope converter, a complete conver-

sion requires the integrator output to "ramp-up" and

"ramp-down."

A simple mathematical equation relates the input sig-

nal, reference voltage, and integration time:

EQUATION 3-1:

For a constant VIN:

EQUATION 3-2:

The dual slope converter accuracy is unrelated to the

integrating resistor and capacitor values, as long as

they are stable during a measurement cycle. An inher-

ent benefit is noise immunity. Noise spikes are inte-

grated, or averaged, to zero during the integration

periods.

Integrating ADCs are immune to the large conversion

errors that plague successive approximation convert-

ers in high-noise environments (see Figure 3-1).

FIGURE 3-1:

BASIC DUAL SLOPE

CONVERTER

3.2

TC7135 Operational Theory

The TC7135 incorporates a system zero phase and

integrator output voltage zero phase to the normal two-

phase dual-slope measurement cycle. Reduced sys-

tem errors, fewer calibration steps, and a shorter over-

range recovery time result.

The TC7135 measurement cycle contains four phases:

System zero

Analog input signal integration

Reference voltage integration

Integrator output zero

Internal analog gate status for each phase is shown in

Figure 3-1.

TABLE 3-1:

INTERNAL ANALOG GATE STATUS

RINTCINT∫

TINT

VIN(T)DT =

VREF TDEINT

RINTCINT

where:

VREF

= Reference voltage

TINT

= Signal integration time (fixed)

TDEINT = Reference voltage integration time

(variable).

VIN =

VREF TDEINT

TINT

REF

Voltage

Analog Input

Signal

Display

Switch

Drive

Control

Logic

Clock

Counter

Polarity Control

Phase

Control

VIN ≈ VREF

Variable

Reference

Integrate

Time

Fixed

Signal

Integrate

Time

Integrator

Comparator

VIN ≈ 1/2 VREF

Conversion Cycle Phase

SWI

SWRI+SWRI-SWZ

SWR

SW1

SWIZ

Reference Figures

System Zero

Closed

Figure 3-2

Input Signal Integration

Closed

Figure 3-3

Reference Voltage Integration

Closed*

Closed

Figure 3-4

Integrator Output Zero

Closed

Figure 3-5

*Note:

Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.

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