W97AH6KB datasheet(1/127 Pages) WINBOND

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W97AH6KB / W97AH2KB

LPDDR2-S4B 1Gb

Publication Release Date: May 15, 2014

Revision: A01-001

- 1 -

Table of Contents-

GENERAL DESCRIPTION ............................................................................................................................................ 6

FEATURES.................................................................................................................................................................... 6

ORDER INFORMATION ................................................................................................................................................ 7

PIN CONFIGURATION .................................................................................................................................................. 8

4.1

134 Ball VFBGA............................................................................................................................................................. 8

4.2

168 Ball WFBGA............................................................................................................................................................ 9

PIN DESCRIPTION ..................................................................................................................................................... 10

5.1

Basic Functionality ....................................................................................................................................................... 10

5.2

Addressing Table ......................................................................................................................................................... 11

BLOCK DIAGRAM ....................................................................................................................................................... 12

FUNCTIONAL DESCRIPTION..................................................................................................................................... 13

7.1

Simplified LPDDR2 State Diagram .............................................................................................................................. 13

7.1.1

Simplified LPDDR2 Bus Interface State Diagram......................................................................................................... 14

7.2

Power-up, Initialization, and Power-Off ........................................................................................................................ 15

7.2.1

Power Ramp and Device Initialization.......................................................................................................................... 15

7.2.2

Timing Parameters for Initialization.............................................................................................................................. 17

7.2.3

Power Ramp and Initialization Sequence .................................................................................................................... 17

7.2.4

Initialization after Reset (without Power ramp) ............................................................................................................. 18

7.2.5

Power-off Sequence .................................................................................................................................................... 18

7.2.6

Timing Parameters Power-Off ..................................................................................................................................... 18

7.2.7

Uncontrolled Power-Off Sequence .............................................................................................................................. 18

7.3

Mode Register Definition.............................................................................................................................................. 19

7.3.1

Mode Register Assignment and Definition ................................................................................................................... 19

7.3.1.1

Mode Register Assignment ............................................................................................................................... 19

7.3.2

MR0_Device Information (MA[7:0] = 00H) ................................................................................................................... 20

7.3.3

MR1_Device Feature 1 (MA[7:0] = 01H)...................................................................................................................... 20

7.3.3.1

Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC).............................................. 21

7.3.3.2

Non Wrap Restrictions ...................................................................................................................................... 21

7.3.4

MR2_Device Feature 2 (MA[7:0] = 02H)...................................................................................................................... 22

7.3.5

MR3_I/O Configuration 1 (MA[7:0] = 03H) ................................................................................................................... 22

7.3.6

MR4_Device Temperature (MA[7:0] = 04H)................................................................................................................. 22

7.3.7

MR5_Basic Configuration 1 (MA[7:0] = 05H) ............................................................................................................... 23

7.3.8

MR6_Basic Configuration 2 (MA[7:0] = 06H) ............................................................................................................... 23

7.3.9

MR7_Basic Configuration 3 (MA[7:0] = 07H) ............................................................................................................... 23

7.3.10

MR8_Basic Configuration 4 (MA[7:0] = 08H) ............................................................................................................... 23

7.3.11

MR9_Test Mode (MA[7:0] = 09H) ................................................................................................................................ 23

7.3.12

MR10_Calibration (MA[7:0] = 0AH) ............................................................................................................................. 24

7.3.13

MR16_PASR_Bank Mask (MA[7:0] = 10H).................................................................................................................. 24

7.3.14

MR17_PASR_Segment Mask (MA[7:0] = 11H)............................................................................................................ 25

7.3.15

MR32_DQ Calibration Pattern A (MA[7:0] = 20H) ........................................................................................................ 25

7.3.16

MR40_DQ Calibration Pattern B (MA[7:0] = 28H) ........................................................................................................ 25

7.3.17

MR63_Reset (MA[7:0] = 3FH): MRW only ................................................................................................................... 25

7.4

Command Definitions and Timing Diagrams................................................................................................................ 26

7.4.1

Activate Command ...................................................................................................................................................... 26

7.4.1.1

Activate Command Cycle: tRCD = 3, tRP = 3, tRRD = 2 ................................................................................... 26

7.4.1.2

tFAW Timing..................................................................................................................................................... 27

7.4.1.3

Command Input Setup and Hold Timing............................................................................................................ 27

7.4.1.4

CKE Input Setup and Hold Timing .................................................................................................................... 28

7.4.2

Read and Write Access Modes.................................................................................................................................... 28

7.4.3

Burst Read Command ................................................................................................................................................. 28

7.4.3.1

Data Output (Read) Timing (tDQSCKmax)........................................................................................................ 29

7.4.3.2

Data Output (Read) Timing (tDQSCKmin)......................................................................................................... 30

Số phần tương tự - W97AH6KB

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Winbond	W9712G6JB	1Mb / 86P	2M 횞 4 BANKS 횞 16 BIT DDR2 SDRAM
Microchip Technology	W9712G6KB25I	1Mb / 56P	SAMA5D2 System in Package (SIP) MPU with up to 1 Gbit DDR2 SDRAM or 2 Gbit LPDDR2 SDRAM 2021
Winbond	W9712G8JB	1Mb / 86P	4M 횞 4 BANKS 횞 8 BIT DDR2 SDRAM
	W971GG6JB	1Mb / 87P	8M ??8 BANKS ??16 BIT DDR2 SDRAM
	W971GG6JB	1Mb / 87P	8M X 8 BANKS X 16 BIT DDR2 SDRAM

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