W97AH6KB datasheet(55/127 Pages) WINBOND

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W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 55 -

Table of Example of Bank and Segment Masking use in LPDDR2-S4 devices

Segment Mask(MR17)

Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7

BankMask (MR16)

Segment 0

Segment 1

Segment 2

Segment 3

Segment 4

Segment 5

Segment 6

Segment 7

Note:

This table illustrates an example of an 8-bank LPDDR2-S4 device, when a refresh operation to bank 1 and bank 7, as well as segment 2 and

segment 7 are masked

7.4.20 Mode Register Read Command

The Mode Register Read command is used to read configuration and status data from mode registers. The Mode

at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r- CA4r}. The mode register

contents are available on the first data beat of DQ[0:7], RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock

where the Mode Register Read Command is issued. Subsequent data beats contain valid, but undefined content,

except in the case of the DQ Calibration function DQC, where subsequent data beats contain valid content as

described in section 7.4.21.2

“DQ Calibration”. All DQS_t, DQS_c shall be toggled for the duration of the Mode

The MRR command has a burst length of four. The Mode Register Read operation (consisting of the MRR command

and the corresponding data traffic) shall not be interrupted. The MRR command period (tMRR) is 2 clock cycles.

Mode Register Reads to reserved and write-only registers shall return valid, but undefined content on all data beats

and DQS_t, DQS_c shall be toggled.

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