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RF65 bảng dữ liệu(PDF) 56 Page - List of Unclassifed Manufacturers

tên linh kiện RF65
Giải thích chi tiết về linh kiện  Low Power Integrated UHF Receiver With -120dBm High Sensitivity
PDF  72 Pages
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nhà sản xuất  ETC2 [List of Unclassifed Manufacturers]
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RF65 bảng dữ liệu(HTML) 56 Page - List of Unclassifed Manufacturers

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Page 56
RF65
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
RegFrfLsb
(0x09)
7-0
Frf(7:0)
rw
RegOsc1
(0x0A)
7
RcCalStart
w
0
Triggers the calibration of the RC oscillator when set.
Always reads 0. RC calibration must be triggered in
Standby mode.
6
RcCalDone
r
1
0
→ RC calibration in progress
1
→ RC calibration is over
5-0
-
r
000001 unused
RegAfcCtrl
(0x0B)
7-6
-
r
00
unused
5
AfcLowBetaOn
rw
0
Improved AFC routine for signals with modulation index
lower than 2. Refer to section 3.4.17 for details
0
→ Standard AFC routine
1
→ Improved AFC routine
4-0
-
r
00000
unused
RegLowBat
(0x0C)
7-5
-
r
000
unused
4
LowBatMonitor
rw
-
Real-time (not latched) output of the Low Battery detector,
when enabled.
3
LowBatOn
rw
0
Low Battery detector enable signal
0
→ LowBat off
1
→ LowBat on
2-0
LowBatTrim
rw
010
Trimming of the LowBat threshold:
000
→ 1.695 V
001
→ 1.764 V
010
→ 1.835 V
011
→ 1.905 V
100
→ 1.976 V
101
→ 2.045 V
110
→ 2.116 V
111
→ 2.185 V
RegListen1
(0x0D)
7-6
ListenResolIdle
rw
10
Resolution of Listen modes timings (calibrated RC osc):
0101
→ 64 us
1010
→ 4.1 ms
1111
→ 262 ms
Others
→ reserved
5-4
ListenResolRx
rw
01
Resolution of Listen mode Rx time (calibrated RC osc):
00
→ reserved
01
→ 64 us
10
→ 4.1 ms
11
→ 262 ms
3
ListenCriteria
rw
0
Criteria for packet acceptance in Listen mode:
0
→ signal strength is above RssiThreshold
1
→ signal strength is above RssiThreshold and
SyncAddress matched
2-1
ListenEnd
rw
01
Action taken after acceptance of a packet in Listen mode:
00
→ chip stays in Rx mode. Listen mode stops and must
be disabled (see section 4.3).
01
→ chip stays in Rx mode until PayloadReady or
Timeout interrupt occurs. It then goes to the mode defined
by Mode. Listen mode stops and must be disabled (see
section 4.3).
10
→ chip stays in Rx mode until PayloadReady or
Timeout interrupt occurs. Listen mode then resumes in
Idle state. FIFO content is lost at next Rx wakeup.
11
→ Reserved
0
-
r
0
unused



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