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PIC17C752-08/CL bảng dữ liệu(PDF) 167 Page - Microchip Technology

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Giải thích chi tiết về linh kiện  High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D
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© 1998 Microchip Technology Inc.
DS30289A-page 167
PIC17C7XX
15.2.15 CLOCK ARBITRATION
Clock arbitration occurs when the master during any
receive, transmit, or repeated start/stop condition
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud
rate generator (BRG) is suspended from counting until
the SCL pin is actually sampled high. When the SCL
pin is sampled high, the baud rate generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device.
(Figure 15-36)
15.2.16 SLEEP OPERATION
While in sleep mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs wake the processor from
sleep ( if the SSP interrupt is enabled).
15.2.17 EFFECTS OF A RESET
A reset disables the SSP module and terminates the
current transfer.
FIGURE 15-36: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
SCL
SDA
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.
SCL line sampled once every machine cycle (Tosc • 4).
Hold off BRG until SCL is sampled high.
T
BRG
T
BRG
T
BRG
to measure high time interval



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