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PIC17C752-08/CL bảng dữ liệu(PDF) 149 Page - Microchip Technology

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PIC17C752-08/CL bảng dữ liệu(HTML) 149 Page - Microchip Technology

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© 1998 Microchip Technology Inc.
DS30289A-page 149
PIC17C7XX
15.2.5
MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
abled. Control of the I2C bus may be taken when the P
bit is set, or the bus is idle with both the S and P bits
clear.
In master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 15-20: SSP BLOCK DIAGRAM (I2C MASTER MODE)
Read
Write
SSPSR
Start bit, Stop bit,
Start bit detect,
SSPBUF
Internal
data bus
Set/Reset, S, P, WCOL (SSPSTAT)
shift
clock
MSb
LSb
SDA
Acknowledge
Generate
Stop bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
SCL
SCL in
Bus Collision
SDA in
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
rate
generator
SSPM3:SSPM0



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