93LC56BSLASHST datasheet(5/12 Pages) MICROCHIP

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93LC56A/B

Preliminary

DS21208A-page 5

3.4

ERASE

The ERASE instruction forces all data bits of the spec-

iﬁed address to the logical “1” state. CS is brought low

following the loading of the last address bit. This falling

edge of the CS pin initiates the self-timed programming

cycle.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical “0” indicates that program-

ming is still in progress. DO at logical “1” indicates that

the register at the speciﬁed address has been erased

and the device is ready for another instruction.

3.5

Erase All (ERAL)

The ERAL instruction will erase the entire memory

array to the logical “1” state. The ERAL cycle is identical

to the ERASE cycle except for the different opcode. The

ERAL cycle is completely self-timed and commences at

the falling edge of the CS. Clocking of the CLK pin is not

necessary after the device has entered the ERAL cycle.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire ERAL cycle is com-

plete.

FIGURE 3-2:

ERASE TIMING

FIGURE 3-3:

ERAL TIMING

CLK

TCSL

CHECK STATUS

AN-1

AN-2

•••

TSV

TCZ

BUSY

READY

HIGH-Z

TWC

HIGH-Z

CLK

TCSL

CHECK STATUS

•••

TSV

TCZ

BUSY

READY

HIGH-Z

TEC

HIGH-Z

Guaranteed at Vcc = 4.5V to +6.0V.

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