TAS2553_15 datasheet(29/58 Pages) TI

29 / 58 page

TAS2553

Host (Baseband /

Apps Processor)

SDA

SCL

MCLK

BCLK

WCLK

DOUT

DIN

MCLK

BCLK

WCLK

DIN

SDA

SCL

OUT-

OUT+

VSENSE-

VSENSE+

Speaker

Output

SDA

SCL

MCLK

BCLK

WCLK

DIN

OUT-

OUT+

VSENSE-

VSENSE+

Speaker

Output

TAS2553

ADDR

IOVDD

DOUT

7-Bit I

2C Address:

0x40

7-Bit I

2C Address:

0x41

TAS2553

www.ti.com

SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

Figure 46. Stereo Configuration with Two TAS2553 DOUT Muxed in TDM Mode

7.4.3 PDM Mode

Set Register 0x03, D(7:6) = 00 to place the TAS2553 audio interface into PDM mode. In PDM mode, the data

stream is a continuous stream of undecimated pulse-modulated data that is 64x the sample rate. Because it is a

continuous stream, frame synchronization is not required and WCLK is not used. Specifying clocks-per-frame is

not required for PDM mode. The PDM input bit clock is IVCLKIN as set in Register 0x11, D(1:0).

The TAS2553 can be configured for I2S input mode and PDM output mode. Figure 47 shows the timing diagram

for PDM input mode. Timing specifications are listed in Table 9 and Table 10.

The TAS2553 clocks PDM input data on either the rising edge or falling edge of IVCLKIN as set in Register

0x11, D(2). The device does not read concurrent data on both edges. Set the I2C register to read either rising

clock edge or falling clock edge data.

Submit Documentation Feedback

Product Folder Links: TAS2553

TAS2553 bảng dữ liệu(PDF) 29 Page - Texas Instruments

TAS2553 bảng dữ liệu(HTML) 29 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

bảng dữ liệu tải về

Link URL