LM49352 datasheet(53/106 Pages) TI

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PCM_CLK

PCM_SDO/

PCM_SDI

PCM_SYNC

Short frame sync mode

Long frame sync mode

I2S_CLK

I2S_SDO/

I2S_SDI

I2S_SYNC

Left Word

Right Word

LM49352

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SNAS467E – MARCH 2009 – REVISED MARCH 2013

Figure 64. Right Justified Data Format (24 bit example)

Figure 65. PCM Serial Data Format (16 bit example)

The following registers are used to control the LM49352's audio ports. Audio Port 1 and Audio Port 2 are

identical. Port 1 is programmed through the (0x5Xh) registers. Port 2 is programmed through the (0x6Xh)

registers.

Table 36. BASIC_SETUP (0x50h/0x60h)

Bits

Field

Description

STEREO

If set, the audio port will receive and transmit stereo data.

RX_ENABLE

If set, the input is enabled (enables the SDI port and input shift register and any clock

generation required).

TX_ENABLE

If set, the output is enabled (enables the SDO port and output shift register and any clock

generation required).

CLOCK_MS

If set, the audio port will transmit the clock when either the RX or TX is enabled.

SYNC_MS

If set, the audio port will transmit the sync signal when either the RX or TX is enabled.

CLOCK_PHASE

This sets how data is clocked by the Audio Port.

CLOCK_PHASE

Audio Data Mode

I2S (TX on falling edge, RX on rising edge)

PCM (TX on rising edge, RX on falling edge)

STEREO_SYNC_PHASE

If set, this reverses the left and right channel data of the Audio Port.

STEREO_SYNC_PHASE

Audio Port Data Orientation

Left channel data goes to left channel output.

Right channel data goes to right channel output.

Right channel data goes to left channel output.

Left channel data goes to right channel output.

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