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MAX6740XKL bảng dữ liệu(PDF) 10 Page - Maxim Integrated Products

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Giải thích chi tiết về linh kiện  Low-Power Dual-/Triple-Voltage SC70 UP Supervisory Circuits
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MAX6740XKL bảng dữ liệu(HTML) 10 Page - Maxim Integrated Products

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Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
10
______________________________________________________________________________________
Detailed Description
Supply Voltages
The MAX6736–MAX6745 µP supervisory circuits main-
tain system integrity by alerting the µP to fault condi-
tions. These devices are optimized for systems that
monitor two or three supply voltages. The reset output
state is guaranteed to remain valid while either VCC1 or
VCC2 is above 1.2V.
Threshold Levels
The MAX6736/MAX6737/MAX6740/MAX6741/MAX6743/
MAX6744 input voltage threshold combinations are indi-
cated by a two-letter code in Table 1. The MAX6738/
MAX6739/MAX6742/MAX6745 input voltage thresholds
are indicated by a one-letter code in Table 2. Contact the
factory for the availability of other voltage thresholds.
Reset Output
The MAX6736–MAX6745 provide an active-low reset out-
put (
RESET). RESET is asserted when the voltage at
either VCC1 or VCC2 falls below the voltage threshold
level, RSTIN drops below the threshold, or
MR is pulled
low. Once reset is asserted, it stays low for the reset time-
out period. If VCC1, VCC2, or RSTIN goes below the reset
threshold before the reset timeout period is completed,
the internal timer restarts. The MAX6736/MAX6738/
MAX6740/MAX6741/MAX6742 have open-drain reset out-
puts, while the MAX6737/MAX6739/MAX6743/MAX6744/
MAX6745 have push-pull reset outputs (Figure 1).
The MAX6740/MAX6741/MAX6742 include a
RESET
output with a manual reset detect function. The open-
drain
RESET output has an internal 50k
Ω pullup to
VCC1. The RESET output is low while the output is
pulled to GND and remains low for at least the manual
reset timeout period after the external GND pulldown is
VTH1
VCC1
GND
GND
tRP
tMRP
GND
POK1
GND
VTH2
VCC2
GND
tPOKP
MR
RESET
SWITCH
BOUNCE
SWITCH
BOUNCE
Figure 1. Timing Diagram



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