UCD3138ARMHT datasheet(57/83 Pages) TI

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3 A – QB1

( DPWM1C )

3 B – QT1

( DPWM2 C)

2 B – QB2

( EDGEGEN )

2 A – QT 2

( EDGEGEN)

QSYN 2,4

–

QSYN 1,3

–

Transformer

Voltage

DPWM 2 AF

DPWM 2 BF

DPWM3 AF

DPWM3 BF

Current

Peak Level

UCD3138A

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SLUSC66B – MARCH 2015 – REVISED MAY 2015

Here is an overview of the key PSFB signals:

X 1 , X 2 , X 3 and Y 1 , Y 2 , Y 3 are sets of moving edges. All other edges are fixed

Figure 7-3. Key PSFB Signals

7.2.3

DPWM Synchronization

DPWM1 is synchronized to DPWM0, DPWM2 is synchronized to DPWM1, and DPWM3 is synchronized to

DPWM2, ½ period out of phase using these commands:

Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave

Dpwm2Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave

Dpwm3Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave

Dpwm0Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

Dpwm1Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

Dpwm2Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL

// Slave to dpwm-0

= 0;

// Slave to dpwm-1

LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL

// Slave to dpwm-2

= 1;

LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL

= 2;

Application, Implementation, and Layout

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