S1721 datasheet(21/42 Pages) SII

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SUPER-SMALL PACKAGE 2-CIRCUIT HIGH RIPPLE-REJECTION LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR

Rev.2.0_00

S-1721 Series

Seiko Instruments Inc.

Operation

1. Basic operation

Figure 23 shows the block diagram of S-1721 Series.

The error amplifier compares the reference voltage (Vref) with Vfb, which is the output voltage resistance-divided by

feedback resistors Rs and Rf. It supplies the gate voltage necessary to maintain the constant output voltage which is

not influenced by the input voltage and temperature change, to the output transistor.

*1.

Parasitic diode

VSS

Current

supply

−

Vfb

Vref

VIN

VOUT

Error

amplifier

Reference voltage

circuit

Figure

2. Output transistor

In the S-1721 Series, a low on-resistance P-channel MOS FET is used as the output transistor.

Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due to inverse

current flowing from the VOUT pin through a parasitic diode to the VIN pin.

S1721 bảng dữ liệu(PDF) 21 Page - Seiko Instruments Inc