ICS874S02I datasheet(7/16 Pages) IDT

tên linh kiện	ICS874S02I

Giải thích chi tiết về linh kiện	One differential clock input pair

PDF	16 Pages

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nhà sản xuất	IDT [Integrated Device Technology]

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ICS874S02I

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

IDT™ / ICS™ LVDS CLOCK GENERATOR

ICS874S02BMI REV. AOCTOBER 16, 2008

Parameter Measurement Information

3.3V LVDS Output Load AC Test Circuit

Static Phase Offset

Output Rise/Fall Time

Differential Input Level

Cycle-to-Cycle Jitter

Output Duty Cycle/Pulse Width/Period

SCOPE

nQx

3.3V±5%

POWER SUPPLY

+–

Float GND

LVDS

VDDA

VDD,

VDDO

nCLK

CLK

nFB_IN

FB_IN

➤t(Ø)

tjit(Ø) =

 t(Ø) – t(Ø) mean= Phase Jitter

t(Ø) mean = Static Phase Offset

Where t(Ø) is any random sample, and t(Ø) mean is the average

of the sampled cycles measured on the controlled edges)

20%

80%

20%

t F

VOD

Q, QFB

nQ, nQFB

VDD

nCLK

CLK

GND

CMR

Cross Points

➤

tcycle n

tcycle n+1

tjit(cc) =

|tcycle n – tcycle n+1|

1000 Cycles

nQ, nQFB

Q, QFB

PERIOD

odc =

x 100%

Q, QFB

nQ, nQFB

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