STC5455 datasheet(52/56 Pages) CONNOR-WINFIELD

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Page 52 of 56 TM121

Rev:P1.3

Date: October 24, 2011

STC5455

Synchronous Clock for SETS

Data sheet

Preliminary

Application Notes

This section describes typical application use of the STC5455 device. The General section applies to all appli-

cation variations.

General

Power and Ground

Well-planned noise-minimizing power and ground are essential to achieving the best performance of the

device. The device requires 3.3V digital power and analog power input.

It is desirable to provide individual 0.1uF bypass capacitors, located close to the chip, for each of the power

input leads, subject to board space and layout constraints.

Ground should be provided by as continuous a ground plane as possible. A separated analog ground plane is

recommended.

Note: Un-used reference inputs must be grounded.

Figure 12: Power and Ground

Master Oscillator

An external 3.3V LVCMOS level clock (generally driven from TCXO or OCXO) is supplied at pin MCLK as mas-

ter clock. TCXO or OCXO should be carefully chosen as required by application. It is recommended that the

oscillator is placed close to the STC5455. Frequency of the master oscillator has four options, see description

of the register MCLK Freq Reset for details.

3.3V digital

power

inputs

Digital ground

Analog ground

3.3V analog

power

inputs

STC5455

VCC

AVCC

MCLK

OCXO/

TCXO

GND

AGND

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