12

Control Characteristics: Transmitter/Receiver

The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted. Typical

values are for Tc = 40°C, Vcc33 = 3.3 V and Vcc25 = 2.5 V.

Parameter

Symbol

Min

Typ

Max

Units

Reference

Control* Input Voltage Hysteresis LVTTL

Vhys

0.4

V

Control* Input Current LVTTL

Iin

-125

125

µA

0 V < Vin < Vcc33

Control* Output Voltage Low LVTTL

Vol

0.4

V

Iol = 2mA

Control* Output Current High-Z

Ioh

-10

10

µA

0 V < Vin < Vcc33

Address Assert Time

100

ms

1

Interrupt Assert Time

200

ms

2, Figure 20

Interrupt Pulse Width

5

µs

3, Figure 20

Interrupt De-assert Time

500

µs

4, Figure 20

Reset Assert Time

100

µs

5, Figure 19

Reset De-assert Time

500

ms

6, Figure 19

Initialization Time TWS Interfaces

500

ms

Figure 18

TWS Data In Set Up Time

0.10

µs

7, Figure 17

TWS Data In Hold Time

0

µs

8, Figure 17

TWS Clock Low to Data Out Valid

0.10

0.90

µs

9, Figure 17

TWS Data Out Hold Time

50

ns

10, Figure 17

TWS Data Output Rise Time

0.30

µs

Figure 17,

Measured

between 0.8V

and 2.0V

TWS Data Output Fall Time

0.30

µs

TWS Interface Timing

See Atmel

Two-Wire

Serial EEPROM,

e.g. AT24C01A

TWS Write Cycle Time

40ms

Notes:

* Control signals include Adr[2:0], IntL, ResetL, SCL and SDA.

1. This is the module response time from a change in module address, Adr[2:0], to response to TWS communication using the new address.

2. This is the module response time from occurrence of interrupt generating event to IntL assertion, Vout:IntL = Vol.

3. Pulse or static level can be selected for IntL. Pulse mode is default. See Memory Map.

4. This is the module response time from clear on read operation, measured from falling SCL edge after stop bit of read transaction, until Vout:IntL =

Voh where IntL is in static mode.

5. Assertion of ResetL activates a complete module reset, i.e. module returns to factory default and non-volatile control settings. While ResetL is Low,

Tx and Rx outputs are disabled and the module does not respond to the TWS interface.

6. This is the response time from ResetL de-assertion to resumption of operation.

7. Data In Set Up Time is measured from Vil(max)SDA or Vih(min)SDA to Vil(max)SCL.

8. Data In Hold Time is measured from Vil(max)SCL to Vil(max)SDA or Vih(min)SDA.

9. Clock Low to Data Out Time is measured from Vil(max)SCL to Vol(max)SDA or Voh(min)SDA.

10. Data Out Hold Time is measured from Vil(max)SCL to Vol(max)SDA or Voh(min)SDA.