2.4GHz to 2.5GHz

Linear Power Amplifier

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7

For a DAC capable of both sourcing and sinking cur-

rents, the full voltage range of the DAC (typically from 0

to +3V) can be used. By substituting the desired values

can be easily calculated.

For a DAC capable of sourcing current only, use equa-

tion 4 to determine the value of resistor R2 for the

desired maximum current. Use equation 1 to determine

the value of resistor R1 for the desired minimum current.

For a DAC capable of sinking current only, set resistors

R1 and R2 to 0 and connect the DAC directly to the

BIAS pin. Use equation 5 to determine the DAC current

Shutdown Mode

Apply logic low to SHDN (pin C2) to place the

MAX2242 into shutdown mode. In this mode, all gain

stages are disabled and supply current typically drops

to 0.5µA. Note that the shutdown current is lowest when

Power Detector

The power detector generates a voltage proportional to

the output power by monitoring the output power using

an internal coupler. It is fully temperature compensated

and allows the user to set the bandwidth with an exter-

nal capacitor. For maximum bandwidth, connect a

47k

Ω resistor from PD_OUT to GND and do not use any

external capacitor.

Applications Information

Interstage Matching and Bypassing

stage amplifiers, and are also part of the interstage

matching networks required to optimize performance

between the three amplifier stages. See the Typical

Application Circuit for the lumped and discrete compo-

nent values used on the MAX2242 EV kit for optimum

interstage matching and RF bypassing. In addition to

RF bypass capacitors on each bias line, a global

bypass capacitor of 22µF is necessary to filter any

paths from the global bypass capacitor (star topology)

to avoid coupling between PA stages. Use the

MAX2242 EV kit PC board layout as a guide.

External Matching

The RFIN port requires a matching network. The RFIN

port impedance is 16–j30 at 2.45GHz. See the Typical

Application Circuit for recommended component values.

The RFOUT port is an open-collector output that must

biasing. A shunt 33pF capacitor to ground is required

at the supply side of the inductor. In addition, a match-

ing network is required for optimum gain, efficiency,

ACPR, and output power. The load impedance seen at

the RFOUT port of the MAX2242 on the EV kit is

approximately 8 + j5

Ω. This should serve as a good

starting point for your layout. However, optimum perfor-

mance is layout dependent and some component opti-

mization may be required. See the Typical Application

Circuit for the lumped and discrete component values

used on the MAX2242 EV kit to achieve this impedance.

Ground Vias

Placement and type of ground vias are important to

achieve optimum gain and output power and ACPR

performance. Each ground pin requires its own through-

hole via (via diameter = 10mils) placed as near to the

device pin as possible to reduce ground inductance

and feedback between stages. Use the MAX2242 EV

kit PC board layout as a guide.

Layout and Thermal Management Issues

The MAX2242 EV kit serves as a layout guide. Use con-

trolled-impedance lines on all high-frequency inputs

and outputs. The GND pins also serve as heat sinks.

Connect all GND pins directly to the topside RF ground.

On boards where the ground plane is not on the com-

ponent side, connect all GND pins to the ground plane

with plated multiple throughholes close to the package.

PC board traces connecting the GND pins also serve

as heat sinks. Make sure that the traces are sufficiently

wide.

UCSP Reliability

UCSP represents a unique packaging form factor that

may not perform equally to a packaged product

through traditional mechanical reliability tests. UCSP

reliability is integrally linked to the user’s assembly

methods, circuit-board material, and usage environ-

ment. The user should closely review these areas when

considering use of a UCSP. Performance through the

operating-life test and moisture resistance remains

uncompromised as it is primarily determined by the

wafer-fabrication process. Mechanical stress perfor-

mance is a greater consideration for a UCSP. UCSPs

are attached through direct solder contact to the user’s

PC board, foregoing the inherent stress relief of a pack-

aged-product lead frame. Solder joint contact integrity

must be considered. Testing done to characterize the