P4C1281-35JM datasheet(4/11 Pages) PYRAMID

4 / 11 page

P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS

Page 4

Document # SRAM136 REV OR

notes:

1. Stresses greater than those listed under MAxIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification

is not implied. Exposure to MAxIMUM rating conditions for extended

periods may affect reliability.

2. Extended temperature operation guaranteed with 400 linear feet per

minute of air flow.

3. Transient inputs with V

IL and IIL not more negative than –3.0V and

–100mA, respectively, are permissible for pulse widths up to 20ns.

4. This parameter is sampled and not 100% tested.

5. WE is HIGH for READ cycle.

6. CE is LOW for READ cycle.

7. ADDRESS must be valid prior to, or coincident with CE transition

LOW.

8. Read Cycle Time is measured from the last valid address to the first

transitioning address.

9. Transition is measured ± 200 mV from steady state voltage prior to

change,withloadingasspecifiedinFigure1. Thisparameterissampled

and not 100% tested.

AC CHARACTERISTICS—WRITE CYCLE

CC = 5V ± 10%, All Temperature Ranges)

(2)

Sym Parameter

-12

-15

-20

-25

-35

-45

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Write Cycle Time

Chip Enable Time to End of Write

Address Valid to End of Write

Address Setup Time

Write Pulse Width

Address Hold Time from End of

Write

Data Valid to End of Write

Data Hold Time

Write Enable to Output in High Z

Output Active from End of Write

AWE

Write Enable to Data-out Valid

(P4C1281)

ADV

Data-in Valid to Data-out Valid

(P4C1281)

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