M30620FCMFP datasheet(17/33 Pages) MITSUBISHI

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Timing

Mitsubishi microcomputers

M16C / 62M Group

(Low voltage version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = – 20oC to 85oC / – 40oC to 85oC

(Note 2), CM15 = “1” unless otherwise specified)

Table 1.26.23. Memory expansion and microprocessor modes

(when accessing external memory area with wait, and select multiplexed bus)

Note 2: Specify a product of –40°C to 85°C to use it.

Symbol

Standard

Measuring condition

Max.

Min.

Parameter

Unit

td(BCLK-AD)

Address output delay time

th(BCLK-AD)

Address output hold time (BCLK standard)

4ns

td(BCLK-CS)

Chip select output delay time

th(BCLK-CS)

Chip select output hold time (BCLK standard)

4ns

th(RD-AD)

Address output hold time (RD standard)

(Note 1)

td(BCLK-RD)

RD signal output delay time

th(BCLK-RD)

RD signal output hold time

th(WR-AD)

Address output hold time (WR standard)

(Note 1)

td(BCLK-WR)

WR signal output delay time

td(BCLK-DB)

Data output delay time (BCLK standard)

th(BCLK-DB)

Data output hold time (BCLK standard)

td(DB-WR)

Data output delay time (WR standard)

(Note 1)

th(BCLK-ALE)

ALE signal output hold time (BCLK standard)

– 4

td(AD-ALE)

ALE signal output delay time (Address standard)

(Note 1)

th(ALE-AD)

ALE signal output hold time(Address standard)

th(BCLK-WR)

WR signal output hold time

0ns

th(RD-CS)

Chip select output hold time (RD standard)

(Note 1)

th(WR-CS)

Chip select output hold time (WR standard)

(Note 1)

td(AD-RD)

Post-address RD signal output delay time

td(AD-WR)

Post-address WR signal output delay time

tdZ(RD-AD)

Address output floating start time

td(BCLK-ALE)

ALE signal output delay time (BCLK standard)

Note 1: Calculated according to the BCLK frequency as follows:

th(RD – AD) =

f(BCLK) X 2

[ns]

th(WR – AD) =

f(BCLK) X 2

[ns]

th(RD – CS) =

f(BCLK) X 2

[ns]

th(WR – CS) =

f(BCLK) X 2

[ns]

td(DB – WR) =

f(BCLK) X 2

– 80

[ns]

X 3

td(AD – ALE) =

f(BCLK) X 2

– 45

[ns]

th(WR – DB) =

f(BCLK) X 2

[ns]

th(WR-DB)

Data output hold time (WR standard)

(Note 1)

Figure 1.26.1

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