LTC1418AIN datasheet(4/28 Pages) LINER

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LTC1418

TI I G CHARACTERISTICS (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fSAMPLE(MAX)

Maximum Sampling Frequency

200

kHz

tCONV

Conversion Time

3.4

µs

tACQ

Acquisition Time

0.3

µs

tACQ + tCONV

Acquisition Plus Conversion Time

3.7

µs

CS to RD Setup Time

(Notes 9, 10)

0ns

↓ to CONVST↓ Setup Time

(Notes 9, 10)

↓ to SHDN↓ Setup Time to Ensure Nap Mode

(Notes 9, 10)

SHDN

↑ to CONVST↓ Wake-Up Time from Nap Mode

(Note 10)

500

CONVST Low Time

(Notes 10, 11)

CONVST to BUSY Delay

CL = 25pF

Data Ready Before BUSY

↑

Delay Between Conversions

(Note 10)

500

Wait Time RD

↓ After BUSY↑

–5

t10

Data Access Time After RD

↓

CL = 25pF

CL = 100pF

t11

Bus Relinquish Time

820

Commercial

Industrial

t12

RD Low Time

t10

t13

CONVST High Time

t14

Delay Time, SCLK

↓ to DOUT Valid

CL = 25pF (Note 9)

t15

Time from Previous Data Remain Valid After SCLK

↓

CL = 25pF (Note 9)

fSCLK

Shift Clock Frequency

(Notes 9, 10)

12.5

MHz

fEXTCLKIN

External Conversion Clock Frequency

(Notes 9, 10)

0.03

4.5

MHz

tdEXTCLKIN

Delay Time, CONVST

↓ to External Conversion Clock Input

(Notes 9, 10)

533

µs

tH SCLK

SCLK High Time

(Notes 9, 10)

tL SCLK

SCLK Low Time

(Notes 9, 10)

tH EXTCLKIN

EXTCLKIN High Time

(Notes 9, 10)

250

tL EXTCLKIN

EXTCLKIN Low Time

(Notes 9, 10)

250

The q denotes specifications which apply over the full operating

temperature range; all other limits and typicals TA = 25°C.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground with DGND and

AGND wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below VSS or above VDD, they

will be clamped by internal diodes. This product can handle input currents

greater than 100mA below VSS or above VCC without latchup.

Note 4: When these pin voltages are taken below VSS they will be clamped

by internal diodes. This product can handle input currents greater than

100mA below VSS without latchup. These pins are not clamped to VDD.

Note 5: VDD = 5V, VSS = 0V or – 5V, fSAMPLE = 200kHz, tr = tf = 5ns unless

otherwise specified.

Note 6: Linearity, offset and full-scale specifications apply for a single-

ended input with AIN

– grounded.

Note 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB

when the output code flickers between 0000 0000 0000 00 and

1111 1111 1111 11.

Note 9: Guaranteed by design, not subject to test.

Note 10: Recommended operating conditions.

Note 11: The falling edge of CONVST starts a conversion. If CONVST

returns high at a critical point during the conversion, it can create small

errors. For best performance ensure that CONVST returns high either

within 2.1

µs after the conversion starts or after BUSY rises.

Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at

0V or 5V. See Power Shutdown.

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