LTC1418AIN datasheet(8/28 Pages) LINER

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LTC1418

FUNCTIONAL BLOCK DIAGRA

14-BIT CAPACITIVE DAC

COMP

REF AMP

2.5V REF

REFCOMP

4.096V

2.5V

CSAMPLE

•

D13

BUSY

CONTROL LOGIC

D2/(CLKOUT)

INTERNAL

CLOCK

SHDN

D0 (EXT/INT)

D4 (EXTCLKIN)

CONVST RD CS

ZEROING SWITCHES

D1/(DOUT)

NOTE: PIN NAMES IN PARENTHESES

REFER TO SERIAL MODE

D3/(SCLK)

VDD: 5V

VSS: 0V FOR UNIPOLAR MODE

– 5V FOR BIPOLAR MODE

AIN

–

VREF

AGND

DGND

1418 BD

–

SUCCESSIVE APPROXIMATION

SHIFT

SER/PAR

MUX

APPLICATIONS INFORMATION

CONVERSION DETAILS

The LTC1418 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 14-bit parallel or serial output. The ADC

is complete with a precision reference and an internal

clock. The control logic provides easy interface to micro-

processors and DSPs (please refer to Digital Interface

section for the data format).

Conversion start is controlled by the CS and CONVST

inputs. At the start of the conversion the successive

approximation register (SAR) is reset. Once a conversion

cycle has begun it cannot be restarted.

During the conversion, the internal differential 14-bit

capacitive DAC output is sequenced by the SAR from the

most significant bit (MSB) to the least significant bit (LSB).

1418 F01

OUTPUT

LATCH

SAR

CDAC

–

VDAC

–

VDAC

–

COMP

D13

HOLD

AIN

–

ZEROING SWITCHES

CSAMPLE

–

CSAMPLE

HOLD

SAMPLE

Figure 1. Simplified Block Diagram

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