6

LTC1283

CC

HARA TERISTICS

A

TYPICALPERFOR

CE

Sample-and-Hold Acquisition

Time vs Source Resistance

Input Channel Leakage Current

vs Temperature

Noise Error

vs Reference Voltage

REFERENCE VOLTAGE (V)

0

0

0.2

0.4

0.6

0.8

1.0

1.2

0.5

1.0

1.5

2.0

LTC1283 • G15

2.5

ACLK = 500kHz

LTC1283 NOISE = 200

AMBIENT TEMPERATURE (°C)

–50

0.01

0.1

1

10

100

–25

0

25

50

LTC1283 • G14

75

100

125

ON

CHANNEL

OFF

CHANNEL

1000

GUARANTEED

PI FU CTIO S

#

PIN

FUNCTION

DESCRIPTION

1-8

CH0-CH7

Analog Inputs

The analog inputs must be free of noise with respect to AGND.

9

COM

Common

The common pin defines the zero reference point for all single-ended inputs. It must be

free of noise and is usually tied to the analog ground plane.

10

DGND

Digital Ground

This is the ground for the internal logic. Tie to the ground plane.

11

AGND

Analog Ground

AGND should be tied directly to the analog ground plane.

12

Negative Supply

13, 14

Reference Inputs

The reference inputs must be kept free of noise with respect to AGND.

15

CS

Chip Select Input

A logic low on this input enables data transfer.

16

Digital Data Output

The A/D conversion result is shifted out of this output.

17

Data Input

The A/D configuration word is shifted into this input.

18

SCLK

Shift Clock

This clock synchronizes the serial data transfer.

19

ACLK

A/D Conversion Clock

This clock controls the A/D conversion process.

20

Positive Supply

This supply must be kept free of noise and ripple by bypassing directly to the analog

ground plane.

I

DAGRA

BLOCK

0.1

1

10

110

LTC1283 • G13

5

0V TO 2.5V INPUT STEP

+

–

+

9

8

7

6

4

3

2

INPUT

SHIFT

REGISTER

SAMPLE-

AND-

HOLD

10-BIT

CAPACITIVE

DAC

20

ANALOG

INPUT MUX

1

2

3

4

5

6

7

8

9

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

16

SCLK

18

CONTROL

AND

TIMING

15

CS

LTC1283 BD

17

14

DGND

10

AGND

11

12

13

COMP

OUTPUT

SHIFT

REGISTER

19

ACLK

10-BIT

SAR