LTC1283CS datasheet(15/24 Pages) LINER

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LTC1283

APPLICATI

I FOR ATIO

Hardware and Software Interface to TI TMS70C42 Processor

Texas Instruments TMS70C42

The TMS70C42 transfers serial data in 8-bit increments,

LSB-first. To accommodate this, the LTC1283 is pro-

grammed for 16-bit word length and LSB-first format. The

10-bit output data is received by the processor as two

8-bit bytes, LSB-first. The LTC1283 fills the final 6 unused

bits (after the MSB) with zeroes.

DOUT from LTC1283 stored in TMS70C42 RAM

LABEL

MNEMONIC

DESCRIPTION

START

DINT

DISABLES ALL INTERRUPTS

MOVP

% > 2A, P0

DISABLE INTERRUPT FLAGS

MOVP

% > 02, P16

DISABLE INTERRUPT FLAGS

MOV

% > 60, B

ADDRESS OF STACK

LDSP

PUT ADDRESS INTO POINTER

MOVP

% > DF, P5

CONFIGURE PORT A

MOVP

% > 08, P6

ENABLE Tx BY SETTING B3 = 1

MOVP

% > 40, P21

RESET THE SERIAL PORT

MOVP

% > 0C, P20

CONFIGURE THE SERIAL PORT

MOVP

% > 00, P24

TURN START BIT OFF

MOVP

% > 00, P21

ENABLE THE SERIAL PORT

MOVP

% > 00, P23

SET SCLK RATE (TIMER 3)

MOVP

% > C0, P24

START TIMER

LOOP

MOV

% > DF, A

LOAD DIN WORD IN A

CALL

SXTNBIT

ROUTINE THAT SHIFTS DATA

MOV

B, R5

PUT FIRST 8 LSBs IN R5

MOV

A, R6

PUT MSBs IN R6

SXTNBIT

ANDP

% > FE, P4

A0 CLEARED (CS GOES LOW)

MOVP

A, P26

PUT DIN INTO TXBUF

LABEL

MNEMONIC

DESCRIPTION

MOVP

% > 40, P24

SCLK OFF (TIMER 3 DISABLED)

MOVP

% > 17, P21

ENABLE SERIAL PORT

MOVP

% > C0, P24

SCLK ON (TRANSFER BEGINS)

MOVP

% > 16, P21

TXEN GOES LOW

MOV

% > 02, A

LOAD COUNTER

WAIT1

DJNZ

A, WAIT1

LOOP WHILE SHIFT OCCURS

NOP

DELAY

MOVP

P25, B

PUT DOUT IN B

MOVP

A, P26

LOAD TXBUF

MOVP

% > 40, P24

SCLK OFF (TIMER 3 DISABLE)

MOVP

% > 17, P21

ENABLE SERIAL PORT

MOVP

% > C0, P24

SCLK ON (TRANSFER BEGINS)

MOVP

% > 16, P21

TXEN GOES LOW

MOV

% > 02, A

LOAD COUNTER

WAIT2

DJNZ

A, WAIT2

LOOP WHILE SHIFT OCCURS

NOP

DELAY

MOVP

P25, A

PUT DOUT IN A

ORP

% > 01, P4

A0 SET (CS GOES HIGH)

RETS

RETURN TO MAIN PROGRAM

Signetics 83CL410

To interface to the 83CL410, (a 3V version of the 80C51)

the LTC1283 is programmed for MSB-first format and 10-

bit word length. The 83CL410 generates CS, SCLK and DIN

on three port lines and reads DOUT on the fourth.

Parallel Port Microprocessors

When interfacing the LTC1283 to an MPU which has a

parallel port, the serial signals are created on the port with

software. Three MPU port lines are programmed to create

the CS, SCLK and DIN signals for the LTC1283. A fourth

port line reads the DOUT line. An example is made of the

Signetics 83CL410.

Hardware and Software Interface to Signetics 83CL410 Processor

DOUT

DIN

SCLK

ACLK

P1.1

P1.2

P1.3

P1.4

ALE

ANALOG

INPUTS

LTC1283

83CL410

LTC1283 • AI17

•

SCLK

DIN

DOUT

SCLK

TXD

RXD

LTC1283

TMS70C42

LTC1283 • AI15

•

ANALOG

INPUTS

LSB

FILL WITH ZEROES

BYTE 1

LTC1283 • AI16

BYTE 2

MSB

DOUT from LTC1283 stored in 83CL410 RAM

MSB*

LSB

LTC1283 • AI18

*B9 IS MSB IN UNIPOLAR OR

SIGN BIT IN BIPOLAR

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