LTC1197CS8 datasheet(10/28 Pages) LINER

10 / 28 page

LTC1197/LTC1197L

LTC1199/LTC1199L

PI FU CTIO S

CS (Pin 1): Chip Select Input. A logic low on this input

enables the LTC1197/LTC1197L/LTC1199/LTC1199L.

Power shutdown is activated when CS is brought high.

+ IN, CH0 (Pin 2): Analog Input. This input must be free of

noise with respect to GND.

– IN, CH1 (Pin 3): Analog Input. This input must be free of

noise with respect to GND.

GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane.

VREF (Pin 5): LTC1197/LTC1197L Reference Input. The

reference input defines the span of the A/D converter and

must be kept free of noise with respect to GND.

DIN (Pin 5): LTC1199/LTC1199L Digital Data Input. The

A/D configuration word is shifted into this input.

DOUT (Pin 6): Digital Data Output. The A/D conversion

result is shifted out of this output.

CLK (Pin 7): Shift Clock. This clock synchronizes the serial

data transfer.

VCC (Pin 8): Positive Supply. This supply must be kept

free of noise and ripple by bypassing directly to the

analog ground plane. For LTC1199/LTC1199L, VREF is

tied internally to this pin.

DAGRA

BLOCK

CSMPL

BIAS AND

SHUTDOWN CIRCUIT

SERIAL PORT

VCC

CLK

DOUT

+ IN (CH0)

– IN (CH1)

MICROPOWER

COMPARATOR

CAPACITIVE DAC

SAR

VREF

GND

PIN NAMES IN PARENTHESES

REFER TO THE LTC1199/LTC1199L

(DIN)

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