UPD750004A datasheet(22/84 Pages) NEC

22 / 84 page

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Fig. 6-1

Clock Generator Block Diagram

Note Instruction execution

Remarks 1. fX = Main system clock frequency

2. fXT = Subsystem clock frequency

Φ = CPU clock

4. PCC: Processor clock control register

5. SCC: System clock control register

6. One clock cycle (tCY) of the CPU clock (

Φ) is equal to one machine cycle of an instruction.

Subsystem

clock generator

Main system

clock generator

Clock timer

•

Basic interval timer (BT)

•

Timer/event counter

•

Timer counter

•

Serial interface

•

Clock timer

•

INT0 noise eliminator

•

Clock output circuit

1/1 to 1/4096

Frequency divider

Selec-

tor

Selec-

tor

Frequency

divider

Oscillator

disable

signal

HALT

Note

STOP

Note

PCC2, PCC3

clear signal

Wait release signal from BT

Standby release signal from

interrupt control circuit

RESET signal

XT1

XT2

SCC

SCC3

SCC0

PCC

PCC0

PCC1

PCC2

PCC3

STOP flip-flop

HALT flip-flop

fXT

1/2

1/16

1/4

WM.3

•

CPU

•

INT0 noise

eliminator

•

Clock

output

circuit











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