DocID027369 Rev 1

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AN4646

Peripheral interconnect matrix

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Figure 2. Master/Slave timer overview

A description of this feature is provided in the Timer synchronization section on RM0368

and RM0383 reference manuals, while all the possible master/slave connections are

described in the TIMx internal trigger connection tables.

2.1.2

From TIM to ADC

Some timers can be used to generate an ADC trigger event.

The timer output can be either TIMx_TRGO signal or TIMx_CHx event. It is input to ADC

EXTSEL[3:0] and JEXTSEL [3:0] signals.

Figure 3: Master TIM/Slave ADC overview gives an overview of the trigger selection and

master mode selection blocks.

Figure 3. Master TIM/Slave ADC overview

ADC synchronization is described in the Conversion on external trigger and trigger polarity

section of RM0368 and RM0383 reference manuals. The connection between timers and

ADCs regular and injected channels is described in External trigger for regular channels and

External trigger for injected channels tables.

2.1.3

From TIM to DMA

Refer to Section 2.6: DMA block.