AN4080 datasheet(19/35 Pages) STMICROELECTRONICS

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AN4080

Clocks

2.5

ADC clock

The ADC clock is either the dedicated 14 MHz RC oscillator (HSI14) or PCLK divided by 2

or 4. When the ADC clock is derived from PCLK, it is in an opposite phase with PCLK. The

14 MHz RC oscillator can be configured by software either to be turned on/off ("auto-off

mode") by the ADC interface or to be always enabled.

2.6

HSI 48 MHz clock

2.6.1

HSI 48 MHz RC oscillator

The internal HSI 48 MHz RC oscillator is mainly dedicated to provide a high-precision

reference clock to the USB by means of a special clock recovery circuitry (see

Section 2.6.2), which could use the USB SOF signal or the LSE or an external pulse to

adjust the frequency. This source can also be used as a system clock source when the

system is in run mode; it is disabled as soon as the system enters in STOP or Standby

mode. The CRS can be enabled or not depending on the status of the USB and the

synchronization source selected.

2.6.2

HSI 48 MHz clock recovery system (CRS)

The clock recovery system is an advanced digital control interface to the internal fine-

granularity trimmable RC oscillator HSI 48. The CRS is a powerful tool for evaluating the

oscillator output frequency based on comparison with a selectable synchronization signal. It

can adjust automatically the oscillator trimming based on the measured frequency error

value, while keeping also the possibility of a manual trimming.

2.7

Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is

enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

•

If a failure is detected on the HSE oscillator clock, the oscillator is automatically

disabled.

–

A clock failure event is sent to the break inputs of TIM1 advanced control timer

and TIM15, TIM16 and TIM17 general purpose timers.

–

An interrupt is generated to inform the software about the failure (clock security

system interrupt CSSI), allowing the MCU to perform recovery operations.

–

CSSI is linked to the Cortex®-M0 NMI (non-maskable interrupt) exception vector.

•

If the HSE oscillator is used directly or indirectly as the system clock (indirectly means

that it is used as the PLL input clock, and the PLL clock is used as the system clock), a

detected failure causes a switch of the system clock to the HSI oscillator and the

disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the

clock entry of the PLL that is being used as a system clock when the failure occurs, the

PLL is disabled too.

For details refer to STM32F0x1/STM32F0x2/STM32F0x8 advanced ARM-based 32-bit

MCUs reference manual (RM0091) available from STMicroelectronics website www.st.com.

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