µPD3788

19

Data Sheet S14664EJ1V0DS00

APPLICATION CIRCUIT EXAMPLE

Remarks 1. Pin 9 (

φ10) and pin 28 (φ20) should be open to decrease the influence of input clock noise to output

signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.

2. The inverters shown in the above application circuit example are the 74AC04.

GND

GND

GND

GND

GND

RB

NC

GND

CLB

NC

NC

NC

NC

2

NC

1

2

GND

NC

NC

1

TG1

NC

NC

TG2

TG3

10

20

1L

PD3788

+

10 F/16 V

0.1 F

+

47 F/25 V

0.1 F

+5 V

+12 V

+

10 F/16 V 0.1 F

+5 V

B4

B6

B5

B1

B3

B2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

2

Ω

2

Ω

2

Ω

2

Ω

2

Ω

2

Ω

2

Ω

2

Ω

47

Ω

47

Ω

47

Ω

2

Ω

10

Ω

1

TG

CLB

RB

2

µµ

µ

µ

µµ

µ

φ

φ

φ

φ

φ

φ

φ

φ

φ

φ

φ

φ

φφ

φ

φφ