Flash memory interface

PM0059

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execution. If this cannot be done safely, it is recommended to flush the caches by setting the

DCRST and ICRST bits in the FLASH_CR register.

Note:

The I/D cache should be flushed only when it is disabled (I/DCEN = 0).

2.5.5

Interrupts

Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables

interrupt generation when an erase or program operation ends, that is when the busy bit

(BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this

case, the end of operation (EOP) bit in the FLASH_SR register is set.

If an error occurs during a program or erase operation request, one of the following error

flags is set in the FLASH_SR register:

•

PGAERR, PGPERR, PGSERR (Program error flags)

•

WRPERR (Protection error flag)

In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_SR register, an

interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.

Note:

If several successive errors are detected (for example, in case of DMA transfer to the Flash

memory), the error flags cannot be cleared until the end of the successive write requests.

Refer to Table 5: Flash interrupt requests for summary of Flash interrupt request.

2.6

Option bytes

2.6.1

Description of user option bytes

The option bytes are configured by the end user depending on the application requirements.

Table 6

shows the organization of these bytes inside the user configuration sector.

Table 5. Flash interrupt requests

Interrupt events

Event flags

Enable control bits

End of operation

EOP

EOPIE

Write protection error

WRPERR

ERRIE

Programming error

PGAERR, PGPERR, PGSERR

ERRIE

Table 6. Option byte organization

Address

[63:16]

[15:0]

0x1FFF C000

Reserved

ROP & user option bytes (RDP & USER)

0x1FFF C008

Reserved

Write protections nWRP