DocID15687 Rev 5

11/29

PM0059

Flash memory interface

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Instruction cache memory

To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction

cache memory. This feature can be enabled by setting the instruction cache enable (ICEN)

bit in the FLASH_ACR register. Each time a miss occurs (requested data not present in the

currently used instruction line, in the prefetched instruction line or in the instruction cache

memory), the line read is copied into the instruction cache memory. If some data contained

in the instruction cache memory are requested by the CPU, they are provided without

inserting any delay. Once all the instruction cache memory lines have been filled, the LRU

(least recently used) policy is used to determine the line to replace in the instruction memory

cache. This feature is particularly useful in case of code containing loops.

Data management

Literal pools are fetched from Flash memory through the D-Code bus during the execution

stage of the CPU pipeline. The CPU pipeline is consequently stalled until the requested

literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB

databus D-Code have priority over accesses through the AHB instruction bus I-Code.

If some literal pools are frequently used, the data cache memory can be enabled by setting

the data cache enable (DCEN) bit in the FLASH_ACR register. This feature works like the

instruction cache memory, but the retained data size is limited to 8 rows of 128 bits.

Note:

Data in user configuration sector are not cacheable.

2.5

Erase and program operations

For any Flash memory program operation (erase or program), the CPU clock frequency

(HCLK) must be at least 1 MHz. The contents of the Flash memory are not guaranteed if a

device reset occurs during a Flash memory operation.

During a write/erase operation to the Flash memory, any attempt to read the Flash memory

will caused the bus to stall. Read operations are processed correctly once the program

operation has completed. This means that code or data fetches cannot be performed while

a write/erase operation is ongoing.

2.5.1

Unlocking the Flash control register

After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the

Flash memory against possible unwanted operations due, for example, to electric

disturbances. The following sequence is used to unlock this register:

1.

Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)

2.

Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)

Any wrong sequence will return a bus error and lock up the FLASH_CR register until the

next reset.

The FLASH_CR register can be locked again by software by setting the LOCK bit in the

FLASH_CR register.

Note:

The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_

SR

register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall

until the BSY bit is cleared.