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PM0051 bảng dữ liệu(PDF) 18 Page - STMicroelectronics |
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PM0051 bảng dữ liệu(HTML) 18 Page - STMicroelectronics |
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18 / 27 page ![]() Programming STM8 Flash microcontrollers PM0051 18/27 Doc ID 14614 Rev 3 Standard block programming The following sequence is required to perform a standard block program sequence (block erased and programmed): 1. Unlock the memory if not already done. The UBC option byte can be read to check if the block to program is not in the UBC area. If necessary, reprogram it to allow erasing and programming the targeted block. 2. Write 0x01 in FLASH_CR2 (PRG bit active), and 0xFE in FLASH_NCR2 (NPRG bit active). 3. Write all the data bytes of the block you want to program starting with the very first address of the block. No read or write access to the program memory is allowed during these load operations as they might corrupt the values to be programmed. The programming cycle starts automatically when all the data in the block have been written. 4. Check the WR_PG_DIS bit in FLASH_IAPSR to verify if the block you attempted to program was not write protected (optional) 5. For devices with RWW capability, poll the HVOFF bit in FLASH_IAPSR register for the start of program operation (high voltage mode). HVOFF is reset when the program operation starts, thus indicating that the memory is ready for RWW. 6. To check if the program operation is complete, poll the EOP bit in FLASH_IAPSR from program memory. EOP is set to ‘1’ when the standard block program operation has completed. To avoid polling the EOP bit, an interrupt can be generated when EOP is set. Note: It is mandatory to execute steps 2 to 5 from RAM. Caution: EOP and WR_PG_DIS bits are cleared by reading the FLASH_IAPSR register. It is consequently strongly recommended to perform one single read operation to the FLASH_IAPSR register to check the values of these bits. Caution: FLASH_CR2 and FLASH_NCR2 must be written consecutively to be taken into account. If only one register is set, both are forced to their reset values, causing the program operation to be performed at byte level. |
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