AN3961 datasheet(28/46 Pages) STMICROELECTRONICS

28 / 46 page

Hardware layout and configuration

AN3961

28/46

DocID022083 Rev 3

externally forcing THSD to a positive low-voltage supply, the thermal protection is

disabled.

–

D_CTR can be used to optimize 2nd HD performance by tuning the fall

propagation delay (TDF - see the STHV748 datasheet for further details). If

D_CTR is equal to ground, TDF has the nominal value. If D_CTR is varied from 2

V to 4.2 V, TDF can be changed from -1 ns to +600 ps, with respect to the nominal

value.

–

EXPOSED-PAD is internally connected to the substrate. It can be floating or

connected to a 100 V capacitance toward ground, in order to reduce noise during

the receiving phase.

The fixed configuration of these pins is described Table 14.

Table 14. STHV748 special pin configuration

Special pins on the demo PCB

Name

Description

Status on board

INT_BIAS

(pin 64)

With INT_BIAS=1, the IC internally generates the

reference voltages on REF_HVP1/0 (pin 7, 10, 39,

42) and REF_HVM1/0 (pin 2, 15, 34, 47). These

voltages are set VDDP below HVP and VDDP

above HVM, respectively:

REF_HVM# = HVM# + VDDP REF_HVP# = HVP#

- VDDP

When INT_BIAS=0, it is required that an external

voltage is applied to REF_HVM# and REF_HVP#

pins

Active – forced to 3 V through

R57=10 k

THSD

(pin 32)

Thermal shutdown pin

Active (J24 closed between 1 to 2 –

forced to 3 V through R58=10 k

Ω).

The user can monitor the THSD

status on TP3 (test point).

Moreover, the user can give the

control to FPGA by shorting J24

between 2 and 3

D_CTR

(pin 16)

Delay control pin

Not active – forced directly to

ground

EXPOSED-PAD

Substrate

Not active – connected to ground

through C82=0.22 µF

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