AN3404

Low power modes

Doc ID 018847 Rev 3

11/30

4.3

Slowing down the clock frequency

In Run mode, choosing the clock frequency is very important to ensure the best compromise

between performance and consumption. The selection is done by programming the

prescaler registers. These registers can also be used to slow down the peripherals before

entering a low power mode.

4.4

Peripheral clock gating (PCG)

Peripheral clock gating (PCG) can be used for additional power saving. This can be done at

any time by selectively enabling or disabling the clock connection to individual peripherals

through the CLK_PCKENRx registers. These settings are effective both in Run and Wait

modes.

Note:

As all peripheral clocks are gated by default after reset on STM8TL5xxx devices, it is

mandatory to enable the clock for a given peripheral before accessing any peripheral

register.

4.5

Execution from RAM

The code can be executed from RAM in order to save power consumption. However, due to

the difference between the size of the data and the instruction bus from Flash (32-bit) and

RAM (8-bit), performance is degraded when executed from RAM. It is important to take into

account the performance and the ratio between Run/Halt operations.

Figure 2 shows the different bus widths for Flash and RAM memories.

Table 2.

Low power mode summary

Low power

modes

Entry

instruction

Functions

Low power mode

consumptions

CPU

Peripherals

HSI

LSI

Flash RAM

STM8TL5xxx

typical values

@ 3 V/25°C

Wait

WFE or

WFI

Off

Can be

enabled

On

On

On

On

500 µA

Active-halt

with

ProxSense

Halt

Off

On

Off

On

1.

Value during an acquisition (see the STM8TL5xxx datasheet) with 1 transmitter and 1 receiver.

Active-halt

with AWU

On

Off

On

1.0 µA

Halt

Off

Off

On

0.4 µA