Using an external clock

AN2674

18/22

Doc ID 14204 Rev 2

Figure 7.

External clock connection to SPEAr3xx

C1 is optional and may be needed for clock sources with extremely fast edges and is in the

range of 10 pF to 33 pF. Some configurations may find that only R1 and R3 are needed (R2

= 0 Ohm).

The clock source IC and the resistor network should be placed as close to SPEAr3xx as

practical to improve signal quality. The resistor values depend on Ro (the output impedance

of the clock source), the rise/fall time of the clock source, and the characteristic impedance

and length of the transmission lines. Because every application has different variables, a

single set of resistor values cannot apply to every situation. The resistor values are sensitive

to Ro, which may not be known accurately from data sheets. Some experimentation may be

necessary to arrive at suitable values and Spice simulations are recommended. Table 6 lists

values that can be used to start evaluation. These are examples of resistor network values

with different output impedances of the clock source. Simulation and measurement of the

actual circuit is strongly recommended.

5.0.3

TDR test traces

Test traces should be add to all PCB designs on all signal layers. A single trace of nominal

impedance between 8 to 15 cm long on each signal layer (it does not have to be straight) is

simple to add to all designs and can always be placed where it does not impact the

functional design, usually along the board perimeter. Include a test point pattern that

matches your TDR probe. The test traces are invaluable to validate PCB impedance

parameters.

5.0.4

Layer order check

A visual feature consisting of stair step numbered windows to verify layer order should be

included in all PCB layouts. This is most commonly located along one edge of the board.

Table 6.

Examples of resistor network values

Ro

R1

R2

R3

Units

50

56

0

330

Ohms

50

56

56

330

Ohms

25

47

47

220

Ohms

15

56

56

220

Ohms