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AN2549 bảng dữ liệu(PDF) 17 Page - STMicroelectronics

tên linh kiện AN2549
Giải thích chi tiết về linh kiện  Porting an application from the ST10F269Zx to the ST10F272Z2
PDF  33 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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AN2549 bảng dữ liệu(HTML) 17 Page - STMicroelectronics

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2.2.1
Hardware impact
None.
2.2.2
Software impact
None if only CLKOUT is needed.
When the CLKOUT function is enabled by setting the CLKEN bit in the SYSCON register, by
default the CPU clock is output on P3.15.
To have access to the XCLKOUTDIV register, and thus to program the clock pre-scaling
factor, the XMISCEN bit in the XPERCON register and the XPEN bit in the SYSCON
register must be set.
2.3
New multiplexer for X-Interrupts
The limited number of XBus interrupt lines of the present ST10 architecture imposes some
constraints on the implementation of the new functionalities. In particular, the additional
XPeripherals XSSC, XASC, XI2C and XPWM need some resources to implement interrupt
and PEC transfer. For this reason, a complex but very flexible multiplexed structure for the
interrupt is proposed. In Figure 2, the principle is represented through a simple diagram,
which shows the basic structure replicated for each of the four X-interrupt vectors (XP0INT,
XP1INT, XP2INT and XP3INT).
It is based on a new 16-bit register XIRxSEL (x = 0,1,2,3), divided into 2 bytes:
●
Higher Byte (XIRxSEL[15:8]) Interrupt Enable bits
●
Lower Byte (XIRxSEL[7:0]) Interrupt Flag bits
Figure 2.
X-Interrupt basic structure
When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL
register) define a mask which controls which sources will be associated with the unique
available vector. If more than one source is enabled to issue the request, the service routine
has to identify the real event to be serviced. This can easily be done by checking the flag
XIRxSEL[7:0] (x = 0, 1, 2, 3)
XIRxSEL[15:8] (x = 0, 1, 2, 3)
XPxIC.IR (x = 0, 1, 2, 3)
70
15
8
IT Source 7
IT Source 6
IT Source 5
IT Source 4
IT Source 3
IT Source 2
IT Source 1
IT Source 0
Enable[7:0]
Flag[7:0]



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